The present invention relates to an electronic device comprising a circuit substrate to which a semiconductor integrated circuit chip is connected by means of a flip chip method employing solder, and to an optical transmission module.
Soldering is widely employed in the assembly of conventional electronic components (devices). However, due to the need to make electronic devices highly dense, miniature and thin, reduction in terminal pitch is progressing rapidly as a result of miniaturization and of an increase in the number of package connecting terminals, but there have been difficulties with conventional soldering techniques in supplying solder accurately to minute electrodes.
Connection techniques for directly mounting a semiconductor integrated circuit chip on a circuit substrate have been developed, among which flip chip method connections (flip chip connections), in which an active chip face of a semiconductor integrated circuit chip is mounted so as to be oriented downward to face a circuit substrate, have become a prominent fabrication method that serves as a means of realizing an improvement in electrical characteristics and structural density.
However, with such a flip chip connection, since the thermal expansion coefficient of the circuit substrate is large in comparison with that of a semiconductor integrated circuit chip, the application of heat leads to a marked change in the shape of the circuit substrate and, in turn, to an increase in the stress on the connection portion thereof, which sometimes results in the connection breaking.
For this reason, conventional flip chip connections employ a resin between the semiconductor integrated circuit chip and the circuit substrate in order to reduce the extent of any change in the substrate shape, to thereby prevent the connection from being broken.
One example of such a flip chip connection is disclosed in Japanese Patent Application Laid-open No. H9-107003. The structure of this publication employs a circuit substrate that has substrate electrodes disposed so as to be capable of electrical connection with protruding electrodes, an electrically conductive binding agent being interposed between the protruding electrodes and these substrate electrodes, and a resin being interposed between the semiconductor integrated circuit chip and the circuit substrate. The process described in this publication forms protruding electrodes for terminal electrodes of the semiconductor integrated circuit chip, and an electrically conductive binding agent is affixed to the tips of these protruding electrodes using a transfer method. Here, the transfer method is a method according to which protruding electrodes are pressed into an electrically conductive binding agent which is contained in a container to a predetermined depth, and, upon vertically raising these protruding electrodes, the electrically conductive binding agent of a predetermined depth is transferred to the protruding electrodes. Next, a resin is applied to the section of the circuit substrate upon which the semiconductor integrated circuit chip is mounted, and the semiconductor integrated circuit chip is mounted atop the circuit substrate from above the resin and then is heat-cured.
In addition, another flip chip method is disclosed in Japanese Patent Application Laid-open No. H8-172114. The structure described in this publication is constituted by forming protruding electrodes for terminals of a semiconductor integrated circuit chip, and solder is employed for the electrodes of the semiconductor substrate, which solder is melted and connected to the protruding electrodes. The process described in this publication involves forming protruding electrodes for terminal electrodes of the semiconductor integrated circuit chip, applying resin to the section on the circuit substrate upon which this semiconductor integrated circuit chip is to be mounted, mounting the semiconductor integrated circuit chip from above the resin, and applying pressure to and heating the semiconductor integrated circuit chip.
These conventional flip chip connection structures are such that, as shown in FIG. 5, one variety of resin 8 is employed to bind a semiconductor integrated circuit chip 1 and a circuit substrate 3, such that the resin 8 provided between the semiconductor integrated circuit chip 1 and the circuit substrate 3, and the resin 8 provided at the outer perimeter of the semiconductor integrated circuit chip are the same, there being no particular regulation of the modulus of elasticity of the resin.
Further, as shown in FIG. 8, one example, in which a resin 8a is provided between the semiconductor integrated circuit chip 1 and the circuit substrate 3 and a different resin 8b is provided at the outer perimeter of the semiconductor integrated circuit chip, is disclosed in the Japanese Patent Application Laid-open No. 2000-327884. This publication features the use of a resin 8a provided between the semiconductor integrated circuit chip 1 and the circuit substrate 3 that contains: (A) epoxy resin: 100 parts by weight, (B) polyorgano silsequioxane 100 to 300 parts by weight, and (C) curing accelerator: 0.01 to 10 parts by weight, and a resin 8b provided at the outer perimeter of the semiconductor integrated circuit chip 1, which is subject to no particular limitations, but for which preferred materials are: epoxy resins, epoxy resins having the same components as the resin 8xcex1 provided between the semiconductor integrated circuit chip 1 and the circuit substrate 3, and epoxy resins having an expansion coefficient below the glass transition temperature of no more than 20 ppm/xc2x0 C.
Furthermore, another example in which a resin 8a is provided between a semiconductor integrated circuit chip 1 and a circuit substrate 3, and a different resin 8b is provided at the outer perimeter of the semiconductor integrated circuit chip 1 is disclosed in the Japanese Patent Application Laid-open No. 2001-35884. This publication features the provision of a resin film between the semiconductor integrated circuit chip 1 and the circuit substrate 3, and a method of covering the outer perimeter of the semiconductor integrated circuit chip 1 or the whole of the semiconductor integrated circuit chip 1 with an insulating resin.
Further, a structure, which is related to the present invention, appears in Japanese Patent Application Laid-open No. H4-137641.
The techniques disclosed in the above-referenced Japanese Patent Application Laid-open No. H8-172114 and Japanese Patent Application Laid-open No. H9-107003 exhibit problems outlined below due to the fact that one variety of resin is employed for the binding of a semiconductor integrated circuit chip and a circuit substrate, such that the resin provided between the semiconductor integrated circuit chip and the circuit substrate, and the resin provided at the outer perimeter of the semiconductor integrated circuit chip are the same.
In other words, in a case where a resin 6 of low elasticity is employed as the resin, as shown in FIG. 6, when heat is applied, the resin 6 of low elasticity cannot restrain a change in shape of the circuit substrate 3, such that the circuit substrate 3 changes greatly in shape, and, as a result of the change in shape of the circuit substrate 3, the connection portion is subjected to stress, which results in the connection breaking within a short time.
In addition, in a case where a resin of high elasticity 5 is employed as the resin, as shown in FIG. 7, when heat is applied, the resin of high elasticity 5 restrains a change in shape of the circuit substrate 3, such that the change in shape of the circuit substrate 3 is limited. However, the stress on the edge portions 9 of the semiconductor integrated circuit chip is large. Further, separation occurs at the interface between the lateral faces of the semiconductor integrated circuit chip 1 and the resin 8b at the outer perimeter of the semiconductor integrated circuit chip. Further, when no such separation occurs at the interface between the lateral faces of the semiconductor integrated circuit chip and the resin 8b at the outer perimeter of the semiconductor integrated circuit chip, the extent of the change in shape of the circuit substrate is relatively large, which means that there is a great amount of stress on the connection portion, which results in the connection breaking.
Furthermore, the techniques described in Japanese Patent Application Laid-open No. 2000-327884 and Japanese Patent Application Laid-open No. 2001-35884 mentioned above, which feature a constitution in which the resin employed between the semiconductor integrated circuit chip and the circuit substrate is different from the resin employed at the outer perimeter of the semiconductor integrated circuit chip, exhibit the problems outlined below.
The approach outlined in Japanese Patent Application Laid-open No. 2000-327884 does not feature any regulation of the resin at the outer perimeter of the semiconductor integrated circuit chip, but rather only features resins as being preferred, namely: epoxy resins, epoxy resins having the same components as the resin provided between the semiconductor integrated circuit chip and the circuit substrate, and epoxy resins having an expansion coefficient below the glass transition temperature of no more than 20 ppm/xc2x0 C. Japanese Patent Application Laid-open No. 2001-35884 only features, as the insulating resin at the outer perimeter of the semiconductor integrated circuit chip, epoxy resins, epoxy acrylate resins, and silicone resins.
In other words, the above publications do not consider the relationship between the modulus of elasticity of the resin provided between the semiconductor integrated circuit chip and the circuit substrate, and the modulus of elasticity of the resin provided at the outer perimeter of the semiconductor integrated circuit chip (or laterally thereon).
Therefore, in the above-mentioned conventional flip chip connections, when a resin 5 of high elasticity is employed at the outer perimeter of the semiconductor integrated circuit chip, the circuit substrate 3 changes in shape as a result of thermal stress, the stress on the edge portions 9 of the semiconductor integrated circuit chip becomes large, and, within a short time, separation occurs at the interface between the lateral faces of the semiconductor integrated circuit chip 1 and the resin 5 provided at the outer perimeter of the semiconductor integrated circuit chip. Therefore, there is a reduction in the restraining force of the resin 5 provided at the outer perimeter of the semiconductor integrated circuit chip that restrains the circuit substrate 3, and the extent of the change in shape of the circuit substrate 3 increases, meaning that the connection portion is subjected to stress, which results in the connection breaking.
Further, a structure is featured in the Japanese Patent Application Laid-open No. H4-137641 that is similar to the structure of the present invention, but that cannot handle heat cycles like those of the present invention.
Furthermore, the present inventors established that the above problems were prominent as a result of applying such a flip chip connection using solder to the mounting of the Driver IC of an optical transmission module, which constitutes one kind of electronic device. This is the case since, unlike other electronic devices, optical transmission modules are widely installed in the ground, on telephone poles or in other locations outdoors, and, unlike other electronic devices, are exposed to heat cycles with severe temperature differences. As a result, in consideration of the above characteristics, the present inventors have devised an optical transmission module, which, even in a case of carrying out a flip chip connection employing solder for the mounting of a Driver IC on a circuit substrate, is highly durable.
In other words, it is an object of the present invention to improve the durability of an electronic device, and, more particularly, the durability of an optical transmission module, by improving the durability to heat cycles of a flip chip connection between a semiconductor integrated circuit chip and an electronic substrate.
An example of an embodiment of an electronic device that is capable of resolving such problems is an electronic device, in which terminals of a semiconductor integrated circuit chip and terminals of a circuit substrate are mounted with solder so as to face one another, whose structure comprises: a first resin, which is disposed between the circuit substrate and a terminal formation face of the semiconductor integrated circuit chip, and a second resin, which is disposed at the outer perimeter of the semiconductor integrated circuit chip, or is disposed laterally thereon, and in which structure the modulus of elasticity employed for the second resin is smaller than the modulus of elasticity for the first resin.
Therefore, when a resin of low elasticity is provided between the semiconductor integrated circuit chip and the circuit substrate, because the extent of the thermally induced shape change of the circuit substrate is then limited, it is possible to make the stress on or warping of the connection portion of the semiconductor integrated circuit chip and the circuit substrate small.
When a resin of high elasticity is provided at the outer perimeter of the semiconductor integrated circuit chip or laterally thereon, as a result of binding using a second resin, even if the thermal stress increases and the circuit substrate changes in shape, since it is possible to thus make the stress acting on the edge portions of the semiconductor integrated circuit chip small, separation between the lateral faces of the semiconductor integrated circuit chip and the resin can be prevented.
This means that it is possible to keep the extent of the change in shape of the circuit substrate small and thereby improve the connection reliability.
Therefore, in order to realize both such effects, according to the present invention, a flip chip structure which comprises a first resin and a second resin is employed, and, furthermore, resins are selected such that the first resin is a resin with higher modulus of elasticity than the modulus of elasticity of the second resin.
Further, the manufacturing method for this electronic device may be one that includes the following steps:
(1) A resin of high elasticity is applied beforehand to the center portion of the position on the circuit substrate in which a semiconductor integrated circuit chip is to be mounted, and the protruding electrodes of the semiconductor integrated circuit chip and the substrate electrodes are aligned.
(2) Following step (1), the semiconductor integrated circuit chip is mounted atop the circuit substrate.
(3) Following step (2), the semiconductor integrated circuit chip and the circuit substrate are heated and the resin of high elasticity is cured by means of a bonding tool to which the semiconductor integrated circuit chip is adsorbed and by means of a substrate stage whereon the circuit substrate is mounted.
(4) Following step (3), a resin of low elasticity is applied to the outer perimeter of the semiconductor integrated circuit chip, and this resin of low elasticity is cured and formed in fillet shapes at the outer perimeter of or laterally on the semiconductor integrated circuit chip.